Semiconductor-on-insulator (SOI) technology was first commercialized in the late 1990s. The defining characteristic of SOI technology is that the semiconductor region in which circuitry is formed is isolated from bulk substrate by an electrically insulating layer. This insulating layer is typically silicon-dioxide. The reason silicon-dioxide is chosen is that it can be formed on a wafer of silicon by oxidizing the wafer and is therefore amenable to efficient manufacturing. The advantageous aspects of SOI technology stem directly from the ability of the insulator layer to electronically isolate the active layer from bulk substrate. As used herein and in the appended claims, the region in which signal-processing circuitry is formed on an SOI structure is referred to as the active layer of the SOI structure.
SOI technology represents an improvement over traditional bulk substrate technology because the introduction of the insulating layer isolates the active devices in an SOI structure which improves their electrical characteristics. For example, the threshold voltage of a transistor is desirously uniform, and is set in large part by the characteristics of the semiconductor material underneath the transistor's gate. If this region of material is isolated, there is less of a chance that further processing will affect this region and alter the threshold voltage of the device. Additional electrical characteristic improvements stemming from the use of the SOI structure include fewer short channel effects, decreased capacitance for higher speed, and lower insertion loss if the device is acting as a switch. In addition, the insulating layer can act to reduce the effects on active devices from harmful radiation. This is particularly important for integrated circuits that are used in space given the prevalence of harmful ionizing radiation outside the earth's atmosphere.
SOI wafer 100 is shown in FIG. 1. The wafer includes substrate layer 101, insulator layer 102, and active layer 103. The substrate is typically a semiconductor material such as silicon. Insulator layer 102 is a dielectric which is often silicon-dioxide formed through the oxidation of substrate layer 101. Active layer 103 includes a combination of dopants, dielectrics, polysilicon, metal layers, passivation, and other layers that are present after circuitry 104 has been formed therein. Circuitry 104 may include metal wiring; passive devices such as resistors, capacitors, and inductors; and active devices such as transistors. As used herein and in the appended claims, the “top” of SOI wafer 100 references top surface 105 while the “bottom” of SOI wafer 100 references bottom surface 106. This orientation scheme persists regardless of the relative orientation of SOI wafer 100 to other frames of reference, and the removal of layers from, or the addition of layers to SOI wafer 100. Therefore, active layer 103 is always “above” insulator layer 102. In addition, a vector originating in the center of active layer 103 and extending towards bottom surface 106 will always point in the direction of the “back side” of the SOI structure regardless of the relative orientation of SOI wafer 100 to other frames of references, and the removal of layers from, or the addition of layers to SOI wafer 100.
SOI devices are imbued with the ability to enhance and preserve the electrical characteristics of their active devices as described above. However, the introduction of the insulator layer creates a significant problem in terms of the device's ability to dissipate heat. Due to the increasing miniaturization of the devices in integrated circuits, a greater number of heat generating devices must be pressed into a smaller and smaller area. In modern integrated circuits, the heat generation density of circuitry 104 can be extreme. The introduction of insulator layer 102 exacerbates this problem because the thermal conductivity of insulator layer 102 is generally much lower than that of a standard bulk substrate. As mentioned previously, silicon-dioxide is the ubiquitous insulator layer in modern SOI technology. At a temperature of 300 degrees Kelvin (K), silicon-dioxide has a thermal conductivity of roughly 1.4 Watts per meter per Kelvin (W/m*K). A bulk silicon substrate at the same temperature has a thermal conductivity of roughly 130 W/m*K. The nearly 100-fold reduction in heat dissipation performance exhibited by SOI technology is highly problematic. A high level of heat in an integrated circuit can shift the electrical characteristics of its devices outside an expected range causing critical design failures. Left unchecked, excess heat in a device can lead to permanent and critical failures in the form of warping or melting materials in the device's circuitry.
The problem of heat dissipation in SOI devices has been approached using variant solutions. One approach involves the deposition of heat channeling pillars from the insulator layer 102 up through active layer 103. In some cases, these heat channeling pillars are formed of metal since metal generally has a much higher thermal conductivity as compared to silicon-dioxide. In some approaches, these pillars are formed of polysilicon so that they do not interfere with the electrical performance of the circuit, while at the same time they provide a thermal path up and away from insulator layer 102. In other approaches, a hole is cut through insulator layer 102 and heat channeling pillars are deposited into the holes. The result of this configuration is to provide a thermal dissipation channel from active layer 103 through holes in insulator layer 102 down to substrate 101. This heat is then dissipated through substrate 101.
Another approach to the problem of heat dissipation in SOI devices involves operating on the wafer from the backside. FIG. 1B illustrates how SOI wafer 100 can be bonded to a handle wafer 107 comprised of handle substrate 108, and handle insulator layer 109. Although this is a common type of handle, insulator layer 109 does not have to be an insulator material as certain modern processes use handle wafers with semiconductor material, or conductive material in place of insulator layer 109. After bonding to the handle wafer, the resultant structure can then be flipped upside down to form the structure shown in FIG. 1B. Under this approach, substrate 101 and insulator layer 102 are then selectively removed from the back of SOI wafer 100. Following the removal of substrate 101, and the selective removal of insulator layer 102, a layer of metal 110 is deposited on the etched regions to allow for a greater degree of thermal conductivity through insulator layer 102. This metal is often used secondarily as a ground wire or informational signal wire for devices in active layer 103 when the integrated circuit is operational. Although the resultant structure exhibits thermal dissipation capabilities that are superior to those of an SOI structure without backside heat dissipation, the fact that the insulator layer is removed directly underneath the active substrate diminishes the advantages of the SOI structure in terms of its ability to preserve and enhance the electrical characteristics of active devices.